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FEBRUARY 2005
PRELIMINARY
XRK4991A
REV. P1.0.2
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
at the clock destination. This feature minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility. FEATURES
FUNCTIONAL DESCRIPTION
The XRK4991A 3.3V High-Speed Low-Voltage Programmable Skew Clock Buffer offers user selectable control over system clock functions to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews and full-swing logic levels (LVTTL). Each output can be hardwired to one of nine delay or function configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs able to skew up to 6 time units from their nominal "zero" skew position. The completely integrated PLL allows external load and transmission line delay effects to be canceled. When this "zero delay" capability is combined with the selectable output skew functions, the user can create output-tooutput delays of up to 12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of a lowfrequency clock that can be multiplied by two or four FIGURE 1. BLOCK DIAGRAM OF THE XRK4991A
TEST PE FB_IN PHASE CLKIN FSEL SELD0 SELD1 Select Inputs SELC0 SELC1 SELB0 SELB1 SELA0 SELA1
FREQ DET FILTER
* Ref input is 5V tolerant * 3 pairs of programmable skew outputs * Low skew: 200ps same pair, 250ps all outputs * Selectable positive or negative edge
synchronization: Excellent for DSP applications
* Synchronous output enable * Output frequency: 3.75MHz to 85MHz * 2x, 4x, 1/2, and 1/4 outputs * 2 skew grades * 3-level inputs for skew and PLL range control * PLL bypass for DC testing * External feedback, internal loop filter * 12mA balanced drive outputs * 32-pin PLCC package * Jitter < 200 ps peak-to-peak (< 25 ps RMS) * Green packaging
VCO AND TIME UNIT GENERATOR
0E QD0 QD1
SKEW SELECT
QC0 QC1 QB0
MATRIX
QB1 QA0 QA1
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRK4991A PRELIMINARY 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
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PRODUCT ORDERING INFORMATION
PRODUCT NUMBER XRK4991AIJ-5 XRK4991ACJ-5 XRK4991ACJ-7 XRK4991AIJ-7 ACCURACY 500 ps 500 ps 750 ps 750 ps OPERATING TEMPERATURE RANGE -40C to +85C 0C to +70C 0C to +70C -40C to +85C
FIGURE 2. PIN OUT OF THE XRK4991
SELC0
4 SELC1 SELD0 SELD1 PE VCCN QD1 QDO GND GND 5 6 7 8 9 10 11 12 13 14 QD1
3
2
1
32
31
SELB1 30 29 28 27 26 SELB0 OE SELA1 1F0 VCCN QA0 QA1 GND GND 25 24 23 22 21 20 QB0
CLKIN
XRK4991A
15 QC0
16 VCCN
17 FB_IN
18 VCCN
2
QB1
TEST 19
FSEL
GND
VCCQ
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PIN DESCRIPTIONS
PIN NAME CLKIN FB_IN FSEL SELA0 SELA1 SELB0 SELB1 SELC0 SELC1 SELD0 SELD1 TEST OE PIN # 1 17 3 26 27 29 30 4 5 7 1 31 28 TYPE I I I I I I I I I DESCRIPTION Reference frequency input. This input supplies the frequency and timing against which all functional variation is measured. PLL feedback input (typically connected to one of the eight outputs). Three-level frequency range select. Set Table 2. Three-level function selects inputs for output pair 1 (QA0, QA0]). Table 3. Three-level function selects inputs for output pair 2 (QB0, QB1). Table 3. Three-level function selects inputs for output pair 3 (QC0, QC1). See Table 3. Three-level function selects inputs for output pair 4 (QD0, QD1). See Table 3. Three-level select. See test mode section under the block diagram descriptions. Synchronous Output Enable. When HIGH, it stops clock outputs (except QC[1:0]) in a "Low" state - QC[1:0] may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and OE is "High", the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set OE "Low" for normal operation. Selectable positive or negative edge control. When "Low"/"High" the outputs are synchronized with the negative/positive edge of the reference clock. Output pair 1. See Table 2. Output pair 2. See Table 2. Output pair 3. See Table 2. Output pair 4. See Table 2. Power supply for output drivers.
PE QA0 QA1 QB0 QB1 QC0 QC1 QD0 QD1 VCCN
8 24 23 20 19 15 14 11 10 9 16 18 25 2 12 13 21 22 32
I O O O O PWR
VCCQ GND
PWR PWR
Power supply for internal circuitry. Ground.
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XRK4991A PRELIMINARY 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER EXTERNAL FEEDBACK
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By providing external feedback, the XRK4991A gives users flexibility with regard to skew adjustment. The FB_IN signal is compared with the input CLKIN signal at the phase detector in order to drive the VCO. Phase differences cause the VCO to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes. TABLE 1: PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
FSEL = LOW Timing Unit Calculation (tU) VCO Frequency Range (FNOM) (1,2) Skew Adjustment Range (3) Max Adjustment: 1/(44 x FNOM) 15 to 35MHz FSEL = MID 1/(26 x FNOM) 25 to 60MHz FSEL = HIGH 1/(16 x FNOM) 40 to 100MHz COMMENTS
+9.09ns +49 +14%
+9.23ns +83 +23%
+9.38ns +135 +37%
ns Phase Degrees % of Cycle Time
Example 1, FNOM = 15MHz Example 2, FNOM = 25MHz Example 3, FNOM = 30MHz Example 4, FNOM = 40MHz Example 5, FNOM = 50MHz Example 6, FNOM = 80MHz NOTES: 1.
tU = 1.52ns tU = 0.91ns tU = 0.76ns tU = 1.54ns tU = 1.28ns tU = 0.96ns tU = 0.77ns tU = 1.56ns tU = 1.25ns tU = 0.78ns
The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FSEL value based on input frequency range allows the PLL to operate in its `sweet spot' where jitter is lowest. The level to be set on FSEL is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at QA[1:0], QB[1:0] and the higher outputs when they are operated in their undivided modes. The frequency appearing at the CLKIN and FB_IN inputs will be the same as the VCO when the output connected to FB_IN is undivided. The frequency of the CLKIN and FB_IN inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided output as the FB_IN input. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed -4tU in addition to whatever skew value is programmed for those outputs. `Max adjustment' range applies to output pairs 3 and 4 where 6tU skew adjustment is possible and at the lowest FNOM value.
2.
3.
4
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TABLE 2: FREQUENCY RANGE SELECT AND tU CALCULATION [1] fNOM (MHZ) tU = 1 / fNOM X N
MAX 30 50 85
WHERE
APPROXIMATE FREQUENCY (MHZ) AT
WHICH tU
FSEL[2,3] LOW MID HIGH
MIN 15 25 40
N=
= 1.0ns
44 26 16
22.7 38.5 62.5
SKEW SELECT MATRIX The skew select matrix is comprised of four independent sections. Each section has two low-skew, high-fanout drivers (Qx[0:1]), and two corresponding three-level function select (SELx[0:1]) inputs. Table 2 below shows the nine possible output functions for each section as determined by the function select inputs. All times are measured with respect to the CLKIN input assuming that the output connected to the FB_IN input has 0tU selected. TABLE 3: PROGRAMMABLE SKEW CONFIGURATIONS [1]
FUNCTION SELECTS SELX1 LOW LOW LOW MID MID MID HIGH HIGH HIGH SELX0 LOW MID HIGH LOW MID HIGH LOW MID HIGH QA[1:0], QB[1:0] -4tU -3tU -2tU -1tU 0tU +1tU +2tU +3tU +4tU OUTPUT FUNCTIONS QC[1:0] Divide by 2 -6tU -4tU -2tU 0tU +2tU +4tU +6tU Divide by 4 QD[1:0] Divide by 2 -6tU -4tU -2tU 0tU +2tU +4tU +6tU Inverted
NOTES: 1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FSEL is determined by the "normal" operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency (fNOM) always appears at QA0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the CLKIN and FB_IN inputs will be fNOM when the output connected to FB_IN is undivided. The frequency of the CLKIN and FB_IN inputs will be fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication by using a divided output as the FB_IN input. When the FSEL pin is selected HIGH, the CLKIN input must not transition upon power-up until VCC has reached 2.8V.
3.
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XRK4991A PRELIMINARY 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER FIGURE 3. TYPICAL OUTPUTS WITH FB_IN CONNECTED TO A ZERO-SKEW OUTPUT [4]
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t0+1tU
t0+2tU
t0+3tU
t0+4tU
t0+5tU
FB_IN SELA-QA[1:0] SELC-QC[1:0] CLKIN SELB-QB[1:0] SELD-QD[1:0] -6tU (N/A) LM -4tU LL LH -3tU LM (N/A) -2tU LH ML -1tU ML (N/A) 0tU MM MM +1tU MH (N/A) +2tU HL MH +3tU HM (N/A) +4tU HH HL +6tU (N/A) HM (N/A) LL/HH DIVIDED (N/A) HH INVERT
NOTES: 4. FB_IN connected to an output selected for "zero" skew (i.e. SELx1 = SELx0 = MID).
TEST MODE The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the XRK4991 to operate as explained briefly above (for testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied LOW through a 100 resistor. This will allow an external tester to change the state of these pins.) If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase locked loop disconnected, and input levels supplied to CLKIN will directly control all outputs. Relative output to output functions are the same as in normal mode. In contrast with normal operation (TEST tied LOW). All outputs will function based only on the connection of their own function select inputs (SELx[1:0]) and the waveform characteristics.
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t0+6tU
t0-6tU
t0-5tU
t0-4tU
t0-3tU
t0-2tU
t0-1tU
t0
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PRELIMINARY XRK4991A 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (5)
Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground DC Input Voltage Output Current into Outputs (LOW) Static Discharge Voltage (per MIL-STD-883, Method 3015) Latch-Up Current. NOTES: 5. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. -65C to +150C -55C to +125C -0.5V to +7.0V -0.5V to +7.0V 64 mA >2001V >200 mA
TABLE 4: DC ELECTRICAL CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE
SYMBOL VIH VIL VIHH VIMM VILL IIN I3 DESCRIPTION Input HIGH Voltage (CLKIN, FB_IN, OE, PE) Input LOW Voltage (CLKIN, FB_IN, OE, PE) Three-Level Input HIGH Voltage [6] Three-Level Input MID Voltage [6] Three-Level Input LOW Voltage [6] Input Leakage Current (CLKIN and FB_IN inputs only) 3-Level Input DC Current (TEST, FSEL) VCC-0.6 VCC/2-0.3 MIN 2.0 MAX VCC 0.8 VCC VCC/2/+0.3 0.6 5 200 50 200 IIPU IIPD VOH VOL NOTES: 6. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched (during operation), the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. Input Pull-Up Current (PE) Input Pull-Down Current (OE) Output HIGH Voltage Output LOW Voltage 2.4 0.55 100 100 UNIT V V V V V A V V CONDITION Guaranteed Logic HIGH (CLKIN, FB_IN, OE, PE Inputs Only) Guaranteed Logic LOW (CLKIN, FB_IN, OE, PE Inputs Only) 3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only VCC = Max. VIN = VCC VIN = VCC/2 VIN = GND VCC = Max VCC = Max VIN = VCC or GND HIGH Level MID Level LOW Level VIN = GND VIN = VCC
VCC = Min., IOH = -12mA VCC = Min., IOL = 12mA
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XRK4991A PRELIMINARY 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER TABLE 5: POWER REQUIREMENTS (VCC = 3.3V + 10% OPERATING RANGE)
SYMBOL ICCQ PARAMETER Quiescent Power Supply Current TEST CONDITIONS VCC=Max., TEST=MID, CLKIN=LOW PE=LOW, OE=LOW, All outputs unloaded ICC ICCD ITOT Power Supply Current per Input HIGH Dynamic Power Supply Current per Output Total Power Supply Current VCC = Max., VIN = 3V VCC = Max., CL = 0pF VCC=3.3V, FCLKIN=20MHz, CL=160pF
(1)
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TYP 8
MAX. 25
UNIT mA
1 55 29
30 90
A A/MHz mA
VCC=3.3V, FCLKIN=33MHz, CL=160pF
(1)
42
VCC=3.3V, FCLKIN=66MHz, CL=160pF(1) NOTE: (1) For eight outputs, each loaded with 20pF.
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TABLE 6: INPUT TIMING REQUIREMENTS
SYMBOL tR, tF tPWC DH CLKIN DESCRIPTION(1) Maximum input rise and fall times, 0.8V to 2V Input clock pulse, HIGH or LOW Input duty cycle Reference Clock Input 3 10 3.75 90 85 MIN. MAX. 10 UNIT ns/V ns % MHz
NOTE: (1) Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
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PRELIMINARY XRK4991A 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
TABLE 7: SWITCHING CHARACTERISTICS (3.3V + 10% OPERATING RANGE)
SYMBOL FNOM tRPWH tRPWL tu
PARAMETER VCO Frequency Range CLKIN Pulse Width HIGH(11) CLKIN Pulse Width LOW(11) Programmable Skew Time Unit
XRK4991A-2 MIN TYP MAX
XRK4991A-5 MIN TYP MAX
XRK4991A-7 MIN TYP MAX
UNIT
See PLL Programmable Skew Range and Resolution Table 3 3 3 3 3 3 ns ns
See Control Summary Table 0.05 0.1 0.25 0.3 0.25 0.5 0.2 0.25 0.5 1.2 0.5 0.9 0.1 0.25 0.6 0.5 0.5 0.5 0.25 0.5 0.7 1.2 0.7 1 0.1 0.3 0.6 1 0.7 1.2 0.25 0.75 1 1.5 1.2 1.7 ns ns ns ns ns ns
tSKEWPR Zero Output Matched-Pair Skew (Qx[1:0])
[1,2,3]
tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tDEV tPD tODCV tPWH tPWL tORISE tOFALL tLOCK tJR
Zero Output Skew (All Outputs) [1, 4] Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs [1, 6] Output Skew (Rise-Fall, Divided-Divided)
[1, 6]
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs) [1, 6] Output Skew (Rise-Fall, Nominal-Divided,
[1, 2]
Device-to-Device Skew [1, 2, 7] CLKIN Input to FB_IN Propagation Delay
[1, 9]
0.75 -0.25 -1.2 0 0 0.25 1.2 2 1.5 0.15 0.15 1 1 1.2 1.2 0.5 0.15 0.15 1 1 -0.5 -1.2 0 0
1.25 0.5 1.2 2.5 3 1.8 1.8 0.5 25 200 0.15 0.15 1.5 1.5 -0.7 -1.2 0 0
1.65 0.7 1.2 3 3.5 2.5 2.5 0.5 25 200
ns ns ns ns ns ns ns ns ps
Output Duty Cycle Variation from 50% [1] Output HIGH Time Deviation from 50% [1,
10]
Output LOW Time Deviation from 50%
[1,11]
Output Rise Time [1] Output Fall Time [1] PLL Lock Time [1,8] Cycle-to-Cycle Output Jitter [1] RMS Peak-to-Peak
25 200
NOTES: 1. All timing and jitter tolerances apply for FNOM > 25MHz. 2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load. 3. tSKEWPR is the skew between a pair of outputs (Qx[1:0]) when all eight outputs are selected for 0tU. 4. tSKEW0 is the skew between outputs when they are selected for 0tU.
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XRK4991A PRELIMINARY 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
5. 6. 7. 8. For XRK4993-2 tSKEW0 is measured with CL = 0pF; for CL = 20pF, tSKEW0 = 0.35ns Max.
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There are 2 classes of outputs: Nominal (multiple of tU delay), and Divided (QC[1:0] only in Divide-by-2 or Divide-by-4 mode). tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.) 8. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at CLKIN or FB_IN until tPD is within specified limits. tPD is measured with CLKIN input rise and fall times (from 0.8V to 2V) of 1ns. Measured at 2V. Measured at 0.8V.
9. 10. 11.
FIGURE 4. AC TEST LOADS AND WAVEFORMS
VCC 150 Output 150 20pF
tORISE
tOFALL
2.0V 0.8V tPWL
tPWH
LVTTL Output Waveform
<1ns 3.0V 2.0V Vth = 1.5V 0.8V 0V LVTTL Input Test Waveform
<1ns
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PRELIMINARY XRK4991A 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
FIGURE 5. AC TIMING DIAGRAM
tREF tRPWH CLKIN tPD FB_IN tJR Any Q tODCV tODCV tRPWL
tSKEWPR, tSKEW0, 1
OTHER Q
tSKEWPR, tSKEW0, 1
tSKEW2
INVERTED Q
tSKEW2
tSKEW3, 4
CLKIN DIVIDED BY 2
tSKEW3, 4
tSKEW3, 4
tSKEW1, 3, 4
CLKIN DIVIDED BY 4
tSKEW2, 4
NOTES: 1. PE: The AC Timing Diagram applies to PE=VCC. For PE=GND, the negative edge of FB_IN aligns with the negative edge of CLKIN, divided outputs change on the negative edge of CLKIN, and the positive edges of the divide-by-2 and the divide-by-4 signals align. Skew: The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with 75 to VCC/2. tSKEWPR: The skew between a pair of outputs (Qx[1:0]) when all eight outputs are selected for 0tU. tSKEW0: The skew between outputs when they are selected for 0tU. tDEV: The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.) tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. tPWH is measured at 2V. tPWL is measured at 0.8V. tORISE and tOFALL are measured between 0.8V and 2V. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at CLKIN or FB_IN until tPD is within specified limits.
2. 3. 4. 5. 6. 7. 8. 9. 10.
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XRK4991A PRELIMINARY 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
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PACKAGE DIMENSIONS
32 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)
Rev. 1.00
D D1 30 x H1
2 1 32
A1 A2
45 x H2 B1
Corner Chamfer
E3
E1
E
B
D2
e 72 deg typ.
C D3
INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.120 0.140 3.05 3.56 A1 0.075 0.095 1.91 2.41 A2 0.020 --0.51 --B 0.013 0.021 0.33 0.53 B1 0.026 0.032 0.66 0.81 C 0.008 0.013 0.19 0.32 D 0.485 0.495 12.33 12.58 D1 0.448 0.454 11.39 11.54 D2 0.400 0.440 10.17 11.18 0.300 typ. 7.62 typ. D3 E 0.585 0.595 14.87 15.11 E1 0.545 0.557 13.85 14.15 E2 0.500 0.540 12.71 13.72 E3 0.400 typ. 10.16 typ. e 0.050 BSC 1.27 BSC H1 0.023 0.029 0.58 0.74 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 Note: The control dimension is in inches.
R A SEATING PLANE
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PRELIMINARY XRK4991A 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
REVISION HISTORY
REVISION # DATE DESCRIPTION
P1.0.0 P1.0.1 P1.0.2
February 2004 Initial release July 2004 Update block diagram.
February 2005 Renamed pins to Exar convention., removed reference to 2.5V operation. Made edits to text.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2004 EXAR Corporation Datasheet February 2005. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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